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general description the max1193 evaluation kit (ev kit) is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the max1191/ max1192/max1193 dual, 8-bit analog-to-digital convert- ers (adcs). the max1191/max1192/max1193 accept ac- or dc-coupled, differential, or single-ended analog inputs. the digital output produced by the adc can be easily captured with a user-provided high-speed logic analyzer or data acquisition system. the ev kit operates from a 3.3v analog and a 2.5v digital power supply. the ev kit includes circuitry that generates a clock signal from an ac sine wave signal provided by the user. the ev kit comes with the max1193 installed. order free samples of the pin-compatible max1191 or max1192 to evaluate these parts. features up to 45msps sampling rate (max1193) ultra-low-power operation single-ended or fully differential input signal configuration ac- or dc-coupled input configuration configurable reference voltage on-board clock-shaping circuit fully assembled and tested also evaluates max1191 and max1192 (ic replacement required) evaluates: max1191/max1192/max1193 max1193 evaluation kit ________________________________________________________________ maxim integrated products 1 19-2958; rev 0; 7/03 component list for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range ic package MAX1193EVKIT 0? to +70? 28-thin qfn designation qty description c1 c6, c9, c19, c21 c27, c29, c31, c33, c35, c37, c39, c41 22 0.1f 10%, 16v x7r ceramic capacitors (0603) tdk c1608x7r1c104k c7, c12, c14, c20 4 1000pf 10%, 50v x7r ceramic capacitors (0603) tdk c1608x7r1h102k c8, c13, c15 3 0.33f 10%, 6.3v x5r ceramic capacitors (0603) tdk c1608x5r0j334k c10, c11, c16, c17 4 22pf 5%, 50v c0g ceramic capacitors (0603) tdk c1608c0g1h220j c18, c36, c38, c40, c42 5 2.2f 10%, 10v tantalum capacitors (a case) avx taja225k010r c28, c30, c32, c34 4 10f 20%, 10v tantalum capacitors (b case) avx tajb106m010r j1 1 header 2 x 10 designation qty description ju1 ju4, ju7, ju8, ju11 7 3-pin headers ju5, ju6, ju9, ju10 4 2-pin headers r1 r4, r18, r31 r40 15 49.9 ? 1% resistors (0603) r5, r6, r41 r44 0 not installed, resistors (0603) r7 r10, r17 5 2k ? 1% resistors (0603) r11 r14 4 24.9 ? 1% resistors (0603) r15, r20 2 4.02k ? 1% resistors (0603) r16 1 5k ? 1/4in potentiometer, 12 turn r19 1 6.04k ? 1% resistor (0603) r21 r30 10 100 ? 1% resistors (0603) r45, r46 0 not installed, resistors (0402) t1, t2 2 rf transformers mini-circuits tt1-6-kk81 u1 1 max1193eti (28-pin tqfn) u2 1 dual cmos differential line receiver (8-pin so), max9113esa note: to evaluate the max1191/max1192, request a free sam- ple with the max1193 ev kit. selector guide part speed (msps) max1191eti 7.5 max1192eti 22 max1193eti 45
evaluates: max1191/max1192/max1193 max1193 evaluation kit 2 _______________________________________________________________________________________ quick start required equipment ? dc power supplies: digital: 2.5v, 100ma analog: 3.3v, 200ma ? function generator with low-phase noise and low jitter for clock input (e.g., hp 8662a) ? two function generators for analog signal inputs (e.g., hp 8662a) ? logic analyzer or data-acquisition system (e.g., hp 1673, hp 16500c) ? analog anti-aliasing filters ? digital voltmeter procedures the max1193 ev kit is a fully assembled and tested surface-mount board. follow the steps below for board operation. do not turn on power supplies or enable function generators until all connections are com- pleted: 1) verify that shunts are installed across pins 2 and 3 of jumpers ju7 and ju8 (fully operational, outputs enabled). 2) verify that no shunts are installed across jumpers ju9 and ju10. 3) verify that a shunt is installed across pins 1 and 2 of jumper ju11 (internal reference mode). 4) connect the logic analyzer to header j1. both channel a and channel b data signal are multi- plexed on header j1. control signal a/ b on pin j1 j11 indicates whether data is from channel a (high) or from channel b (low). 5) connect a 3.3v power supply to the va and vadut pads. connect the ground terminal of this supply to the gnd pad. 6) connect a 2.5v power supply to the vdb and vodut pads. connect the ground terminal of this supply to the ognd pad. 7) turn on both power supplies. 8) with a voltmeter, verify that 1.38v is measured across test point tp1 and gnd. if the voltage is not 1.38v, adjust potentiometer r16 until 1.38v is obtained. 9) connect the clock function generator to the clkin sma connector. 10) connect the output of the analog signal function generator to the input of the suggested anti-alias- ing filters: a) to evaluate differential ac-coupled analog sig- nals, verify that shunts are installed on pins 2 and 3 of jumpers ju1 ju4. connect the output of the analog anti-aliasing filters to the d/e_ina and d/e_inb sma connectors. b) to evaluate single-ended ac-coupled analog signals, verify that shunts are installed on pins 1 and 2 of jumpers ju1 ju6. verify that resistors r5 and r6 are open. connect the output of the anti-aliasing filters to the s/e_ina+ and s/e_inb+ sma connectors. component list (continued) designation qty description u3 1 buffer/drivers tri-state output (48-pin tssop) texas instruments sn74alvch16244dgg c lkin , d /e _in a, d /e _in b, s /e _in a+ , s /e _in a- , s /e _in b+ , s /e _in b- 7 sma pc-mount connectors none 11 shunts (ju1 ju11) none 1 max1193 pc board note: please indicate that you are using the max1193 when contacting these component suppliers. component suppliers supplier phone fax website avx 843-946-0238 843-626-3123 www.avxcorp.com mini-circuits 718-934-4500 718-934-7092 www.minicircuits.com tdk 847-803-6100 847-390-4405 www.component.tdk.com texas instruments 972-644-5580 214-480-7800 www.ti.com
evaluates: max1191/max1192/max1193 max1193 evaluation kit _______________________________________________________________________________________ 3 c) to evaluate single-ended dc-coupled analog signals, verify that shunts are installed on pins 1 and 2 of jumpers ju2 and ju3, and no shunts are installed on jumpers ju1, ju4, ju5 and ju6. remove capacitors c2 and c3 and resistors r2 and r3. install 0 ? resistors on the r5 and r6. connect the outputs of the anti-aliasing filters to the s/e_ina+ and s/e_inb+ sma connectors. d) to evaluate differential dc-coupled analog sig- nals, verify that shunts are installed on pins 1 and 2 of jumpers ju2 and ju3, and no shunts are installed on jumpers ju1, ju4, ju5, and ju6. remove capacitors c2 and c3 and resis- tors r2 and r3. install 0 ? resistors on the r5 and r6. connect the outputs of the anti-aliasing filters to the s/e_ina+/- and s/e_inb+/- sma connectors. 11) enable the function generators. set the clock func- tion generator for an output amplitude of 2.4v p-p (+11.6dbm) and a frequency (f clk ) of 45mhz. set the analog input signal generators to the desired output test signal amplitudes and frequencies. the two function generators should be phase locked to each other. 12) channel a data is presented on the falling edge and channel b data is presented on the rising edge of the logic analyzer clock. 13) enable the logic analyzer, and begin collecting data. detailed description the max1193 ev kit is a fully assembled and tested cir- cuit board that contains all the components necessary to evaluate the performance of the max1191/max1192/ max1193 dual 8-bit adcs. the adcs provide the digi- tized data of their two input channels in multiplexed fash- ion on a single 8-bit bus. the ev kit comes with the max1193 installed, which can be evaluated with a maxi- mum clock frequency (f clk ) of 45mhz. the max1193 accepts differential or single-ended analog input signals. with the proper board configuration (as specified below), the input signals can be ac- or dc-coupled. the ev kit is based on a four-layer pc board design to optimize the performance of the max1193. separate ana- log and digital power planes minimize noise coupling between analog and digital signals. for simple operation, the ev kit is specified to have 3.3v and 2.5v power sup- plies applied to analog and digital power planes, respec- tively. however, the digital plane can be operated from 1.8v to 3.3v without compromising performance. the logic analyzer s threshold must be adjusted accordingly. access to the digital outputs is provided through head- er j1 for channels a and b. the 0.1in 20-pin header easily interfaces with a user-provided logic analyzer or data acquisition system. power supplies the max1193 ev kit requires separate analog and digital power supplies for best performance. a 3.3v power sup- ply is used to power the analog portion of the max1193 (vadut) and the on-board clock-shaping circuit (va). the max1193 analog supply voltage has an operating range of 2.7v to 3.6v. note that 3.3v must be supplied to the va pads to meet the minimum supply voltage of the clock-shaping circuit. a separate 2.5v power supply is used to power the digital portion (vodut and vdb) of the max1193 and the buffer/driver (u3); however, it can operate with a supply voltage as low as 1.8v and as high as 3.6v. the digital power-supply voltage must not exceed the analog power-supply voltage. clock an on-board clock-shaping circuit generates a clock signal from an ac sine-wave signal applied to the clkin sma connector. the input signal should not exceed a magnitude of 2.6v p-p (+12.3dbm). the fre- quency of the signal should not exceed 45mhz for the max1193. the frequency of the sinusoidal input signal determines the sampling frequency of the adc. differential line receiver u2 processes the input signal to generate the cmos clock signal. the signal s duty cycle can be adjusted with potentiometer r16. a clock signal with a 50% duty cycle (recommended) can be achieved by adjusting r16 until 1.38v (40% of the ana- log power supply) is produced across test points tp1 and gnd when the analog supply voltage is set to 3.3v. the clock signal is available at the header pin j1- 1, which can be used as a clock source for the logic analyzer. additionally, the signal pin j1-11 (a/ b ) is an image of the clock signal. input signals the max1193 accepts differential or single-ended, ac- dc-coupled analog input signals. the ev kit accepts input signals with full-scale amplitude of less than 1.024v p-p (+4dbm). see table 1 for proper jumper configuration. note: when a differential signal is applied to the adc, the positive and negative input pins of the adc each receive half of the input signal supplied at sma con- nectors d/e_ina and d/e_inb with a dc offset voltage of vadut/2.
evaluates: max1191/max1192/max1193 max1193 evaluation kit 4 _______________________________________________________________________________________ table 1. single-ended/differential, ac-/dc-coupled jumper configuration jumper shunt position pin connection ev kit operation ju1 1 and 2 ina- pin connected to com pin through r11 ju2 1 and 2 ina+ pin ac-coupled to sma connector s/e_ina+ through r12 and c2 ju5 installed ina+ pin assumes the dc offset at the refp and refn common analog input signal is applied to channel a. single-ended input, ac-coupled. r5 opened (default) ju1 not installed ina- pin assumes no dc offset ju2 1 and 2 ina+ pin dc-coupled to sma connector s/e_ina+ through r12 and r5 ju5 not installed ina+ pin assumes the dc offset from the analog input source analog input signal is applied to channel a. single-ended input, dc-coupled. r5 shorted (0 ? )) c2 opened (removed) r2 opened (removed) ju1 2 and 3 ina- pin connected to low-side of transformer t1 through r11 ju2 2 and 3 ina+ pin connected to high-side of transformer t1 through r12 analog input signal is applied to channel a. differential input, ac-coupled. ju1 not installed ina- pin dc-coupled to sma connector s/e_ina- through r11 ju2 1 and 2 ina+ pin dc-coupled to sma connector s/e_ina+ through r12 and r5 ju5 not installed ina+ pin assumes the dc offset from the analog input source analog input signal is applied to channel a. differential input, dc-coupled. r5 shorted (0 ? )) c2 opened (removed) r2 opened (removed) ju3 1 and 2 inb+ pin ac-coupled to sma connector s/e_inb+ through r13 and c3 ju4 1 and 2 inb- pin connected to com pin through r14 ju6 installed inb+ pin assumes the dc offset at the refp and refn common analog input signal is applied to channel b. single-ended input, ac-coupled. r6 opened (default) ju3 1 and 2 inb+ pin dc-coupled to sma connector s/e_inb+ through r13 and r6 ju4 not installed inb- pin assumes no dc offset ju6 not installed inb+ pin assumes the dc offset from the analog input source analog input signal is applied to channel b. single-ended input, dc-coupled. r6 shorted (0 ? )) c3 opened (removed) r3 opened (removed) ju3 2 and 3 inb+ pin connected to high side of transformer t1 through r13 ju4 2 and 3 inb- pin connected to low side of transformer t1 through r14 analog input signal is applied to channel b. differential input, ac-coupled.
evaluates: max1191/max1192/max1193 max1193 evaluation kit _______________________________________________________________________________________ 5 power-down/standby/ idle/operating modes the max1193 ev kit also features jumpers that allow the user to enable or disable certain functions of the data converter. jumpers ju7 and ju8 control the power-down, standby, idle, and operating modes of the max1193 ev kit. see table 2 for jumper settings. reference modes the max1193 ev kit provides three modes of operation for the reference: internal reference, buffered external reference, and unbuffered external reference modes. in internal reference mode, the refin pad is connected to vadut. in buffered external reference mode, an external user-provided reference voltage of 1.024v may be connected at the refin pad. in unbuffered external reference mode, refin is connected to gnd, and three external reference voltages should be used to drive refp, refn, and com. jumper ju11 selects the reference modes of the max1193 ev kit. see table 3 for jumper settings. table 1. single-ended/differential, ac-/dc-coupled jumper configuration (continued) table 2. power-down/standby/idle/operating mode configurations jumper shunt position pin connection ev kit operation ju3 1 and 2 inb+ pin dc-coupled to sma connector s/e_inb+ through r13 and r6 ju4 not installed inb- pin dc-coupled to sma connector s/e_inb- through r14 ju6 not installed inb+ pin assumes the dc offset from the analog input source analog input signal is applied to channel b. differential input, dc-coupled. r6 shorted (0 ? ) c3 opened (removed) r3 opened (removed) jumper shunt position pin connection ev kit operation ju7 1 and 2 pd0 connected to ognd ju8 1 and 2 pd1 connected to ognd max1193 in power-down mode adc off, ref off, output three-stated ju7 1 and 2 pd0 connected to ognd ju8 2 and 3 pd1 connected to vodut max1193 in standby mode adc off, ref on, output three-stated ju7 2 and 3 pd0 connected to vodut ju8 1 and 2 pd1 connected to ognd max1193 in idle mode adc on, ref on, output three-stated ju7 2 and 3 pd0 connected to vodut ju8 2 and 3 pd1 connected to vodut max1193 in operating mode adc on, ref on, output enabled ju7, ju8 none pd0, pd1 pads connected to external control source (ttl/cmos compatible) pd0, pd1 = 00; power-down mode pd0, pd1 = 01; standby mode pd0, pd1 = 10; idle mode pd0, pd1 = 11; operting mode table 3. reference modes configuration (jumper ju11) shunt position refin pin connection ev kit operation 1 and 2 connected to vadut internal reference mode. v ref = v refp - v refn = 0.512v 2 and 3 connected to gnd unbuffered external reference mode. refp, refn, com pins driven by external sources none connected to external reference source (1.024v) buffered external reference mode. v ref = v refp - v refn = 0.512v
evaluates: max1191/max1192/max1193 digital output format the max1193 features a single 8-bit, multiplex cmos- compatible digital output bus. channel a is available at the output during a/ b high. channel b is available at the output during a/ b low. the channel selection signal (a/ b ) is an image of the clock that may be used to syn- chronize the output data. refer to the max1193 data sheet for more information. a driver is used to buffer the adc s digital outputs. this buffer is able to drive large capacitive loads, which may be present at the logic analyzer connection, with- out compromising the digital output signals. the out- puts of the buffers are connected to header j1 located on the right side of the ev kit, where the user can con- nect a logic analyzer or data-acquisition system. see table 4 for channel and bit locations on header j1. all even-number pins on header j1 are connected to ognd. max1193 evaluation kit 6 _______________________________________________________________________________________ table 4. header j1 output bit location (multiplexed output operation) channel a/ b bit d0 bit d1 bit d2 bit d3 bit d4 bit d5 bit d6 bit d7 a (clk )* 1 j1-3 a0 j1-5 a1 j1-7 a2 j1-9 a3 j1-13 a4 j1-15 a5 j1-17 a6 j1-19 a7 b (clk )* 0 j1-3 b0 j1-5 b1 j1-7 b2 j1-9 b3 j1-13 b4 j1-15 b5 j1-17 b6 j1-19 b7 * trigger signal for the logic analyzer.
evaluates: max1191/max1192/max1193 max1193 evaluation kit _______________________________________________________________________________________ 7 max1193 u1 max9113 u2 r22 100 ? 1% r21 100 ? 1% 14 d6 13 d7 25 com 24 refin 1 ina- 2 ina+ r23 100 ? 1% 15 d5 r24 100 ? 1% 16 d4 r25 100 ? 1% 17 a/b r26 100 ? 1% 18 d3 r27 100 ? 1% 19 d2 r29 100 ? 1% r45 short ju9 vadut c36 2.2 f 10v c35 0.1 f 21 d0 r28 100 ? 1% 20 d1 28 vdd vodut c42 2.2 f 10v c41 0.1 f 12 ovdd vadut c38 2.2 f 10v c26 0.1 f c37 0.1 f 8 vdd r46 short vadut c40 2.2 f 10v c39 0.1 f 9 vdd 3 gnd 10 gnd 11 ognd 5 gnd u3 sn74alvch16244 r31 49.9 ? 1% j1?9 j1?7 j1?5 j1?3 j1?1 j1? j1? j1? j1? j1? j1?0 j1?8 j1?6 j1?4 j1?2 j1?0 j1? j1? j1? j1? header 2 x 10 j1 2 1y1 47 1a1 44 1a3 46 1a2 43 1a4 41 2a1 40 2a2 38 2a3 37 2a4 36 3a1 r32 49.9 ? 1% 3 1y2 r33 49.9 ? 1% 5 1y3 r34 49.9 ? 1% 6 1y4 r35 49.9 ? 1% 8 2y1 r36 49.9 ? 1% 9 2y2 r37 49.9 ? 1% 11 2y3 r39 49.9 ? 1% 13 3y1 r38 49.9 ? 1% 12 2y4 r40 49.9 ? 1% 14 3y2 1 10e 48 20e 25 30e 24 40e 4 gnd 10 gnd 15 gnd 21 gnd 28 gnd 34 gnd 39 gnd 45 gnd 19 4y1 20 4y2 22 4y3 23 4y4 7 v cc 18 v cc 31 v cc 42 v cc 33 3a3 32 3a4 30 4a1 29 4a2 27 4a3 c25 0.1 f c24 0.1 f c23 0.1 f vdb 26 4a4 16 3y3 17 3y4 35 3a2 3a2 r30 100 ? 1% r1 49.9 ? 1% r7 2k ? 1% r10 2k ? 1% r9 2k ? 1% r8 2k ? 1% r2 49.9 ? 1% r5 open r11 24.9 ? 1% r12 24.9 ? 1% d/e_ina s/e_ina- 1 2 ju1 ju2 refn refp pdo vodut refn refn ju5 3 1 2 3 ju3 ju7 1 1 2 3 6 t1 5 4 1 2 3 com com c1 0.1 f c2 0.1 f c5 0.1 f c10 22pf c11 22pf c13 0.33 f c12 1000pf c15 0.33 f c14 1000pf c8 0.33 f c7 1000pf c9 0.1 f ju6 r13 24.9 ? 1% c16 22pf s/e_ina+ r4 49.9 ? 1% r14 24.9 ? 1% d/e_inb s/e_inb- 1 2 ju4 3 2 3 6 t2 5 4 1 2 3 com clk c4 0.1 f c6 0.1 f c31 0.1 f c32 10 f 10v c17 22pf r3 49.9 ? 1% r6 open c3 0.1 f s/e_inb+ pd1 vodut ju8 ju10 1 2 3 com vdb r41 open r42 open r43 open r44 open ognd c33 0.1 f c34 10 f 10v vodut ognd refin vadut ju11 1 2 3 vdb c27 0.1 f c28 10 f 10v va gnd va c29 0.1 f c30 10 f 10v vadut gnd vadut vodut c19 0.1 f c18 2.2 f 10v c20 1000pf r20 4.02k ? 1% r19 6.04k ? 1% r15 4.02k ? 1% r17 2k ? 1% r18 49.9k ? 1% clk 3a2 7 8 6 5 4 1 2 3 gnd rout2 rout1 v cc rin2+ rin1+ rin2- rin1- va va c21 0.1 f tp1 r16 5k ? 1 2 3 c22 0.1 f clkin va 26 refn 27 refp 6 inb+ 7 inb- 23 pd0 22 pd1 4 clk figure 1. max1193 ev kit schematic
evaluates: max1191/max1192/max1193 max1193 evaluation kit 8 _______________________________________________________________________________________ figure 2. max1193 ev kit component placement guide?omponent side
evaluates: max1191/max1192/max1193 max1193 evaluation kit _______________________________________________________________________________________ 9 figure 3. max1193 ev kit pc board layout?omponent side
evaluates: max1191/max1192/max1193 max1193 evaluation kit 10 ______________________________________________________________________________________ figure 4. max1193 ev kit pc board layout?round plane
evaluates: max1191/max1192/max1193 max1193 evaluation kit ______________________________________________________________________________________ 11 figure 5. max1193 ev kit pc board layout?ower plane
evaluates: max1191/max1192/max1193 max1193 evaluation kit 12 ______________________________________________________________________________________ figure 6. max1193 ev kit pc board layout?older side
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 13 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. evaluates: max1191/max1192/max1193 max1193 evaluation kit figure 7. max1193 ev kit component placement guide?older side

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